"One Less Than 360"

GMS/359: Building a Mainframe on an FPGA

I've started a new project that's been brewing in my mind for years: building a System/360-inspired computer on a modern FPGA. Not a cycle-accurate emulator, not a software simulator — actual hardware, with real registers, real channels, and real blinking lights.

Why "359"? Because this is deliberately *less* than the mighty IBM System/360. It's a humble subset, a teaching machine, a love letter to the mainframe era written in VHDL.

The target platform: Cologne Chip GateMate A1-EVB — a small, affordable FPGA board with enough resources for a respectable retro computer.

Key design decisions made today:

1. Little-endian byte order. Yes, the real S/360 was big-endian. But for practical debugging with modern tools, little-endian makes hex dumps much more readable. We're *inspired by*, not *compatible with*, the original.

2. Opcode-first instruction format. When you look at a memory dump, `9C 00 10 00` immediately tells you "SIO to device 10h" — the opcode jumps out at you.

3. Channel-based I/O. This is non-negotiable. The whole point is to experience what mainframe I/O felt like — the CPU issues SIO, the channel takes over, DMA happens, interrupts fire. No memory-mapped I/O cheating!

 

The component naming follows IBM conventions: GMS 2050 (CPU), GMS 2291 (Video Controller), GMS 2870 (Multiplexor Channel), etc. Each will be a separate VHDL entity, connected via WishBone bus.

Tomorrow: the video controller. Let's put some characters on screen.