The semester is in full swing. The VHDL verification course at ESISAR is focused on testbenches - how to simulate your designs before committing them to hardware. Useful stuff, and I'm finally starting to understand why people write so much infrastructure code that never ends up in the final synthesis
This week we were introduced to the Digilent Zybo Z7-010 board and the Xilinx Vivado/Vitis toolchain. The workflow is impressive, in a way: you drag blocks onto a diagram, connect them with wires, and the tools generate everything - including C header files with register addresses so your ARM code can talk to the hardware you just "designed." Click, click, done.
Powerful? Certainly. But watching the demonstration, I felt a growing unease. The diagram was full of IP blocks - black boxes with inputs and outputs, doing... something. What exactly? How? The tools hide this from you, and you're expected to trust them.
I've spent too many years in software development to be comfortable with that. The methodologies I value - open source, understanding what your code does, being able to trace problems to their source - these don't stop applying just because we've moved from software to hardware.
So I've been reading about the GateMate toolchain instead. Synthesis with Yosys and GHDL. Verification with the same open tools. Place-and-route with nextpnr. Flashing with openFPGALoader. Everything open, everything inspectable. No vendor lock-in, no black boxes, no "trust us, it works."
The GateMate board is still sitting on my desk at home. I haven't touched it since August. But the approach is becoming clearer: when I do start working on it seriously, I want to understand every bit.
December is approaching.
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