Channel I/O Lives

"НЕЛЛО GMS/359!" — Three Days to a Working Mainframe

Day four. Multi-device channel I/O is operational.

 

The video controller (device 10h) and UART (device 12h) both work through the Multiplexor Channel. The CPU sets up a Channel Address Word pointing to Channel Command Words in memory, issues SIO, and the channel does the rest — fetching data, transferring it to the device, decrementing counts, all autonomously.

        ; Set up CAW pointing to CCW at 0300h
        MVI  [48h], 00h
        MVI  [49h], 03h
        MVI  [4Ah], 00h
        SIO  10h              ; Start I/O to video
POLL:   TIO  10h              ; Test I/O
        BB   POLL             ; Branch if Busy
        ...

That TIO/BC polling loop — that's how real mainframe programmers waited for I/O completion before interrupts were set up. Now I can do it too.

The BC instruction

Branch on Condition (opcode 47h) uses a 4-bit mask compared against the 2-bit condition code. The mapping is `mask = 8 >> CC` in IBM's bit numbering. For "Branch if Busy" (CC=2), the mask is 4. We added the extended mnemonic "BB" for readability.

The dual-area display

Rows 0-24: main display area (gray on black).  
Rows 25-29: console area (sky-blue on purple background).

Just like real mainframe terminals had a status line separated from the working area. The console area will eventually show system messages, CPU status, channel activity.

A small bug, a fun story

After "IPL OK", the first channel message appeared as "HЕЛЛО GMS/359" (yes, because of KOI-7 and because it was coded as "Hello") — but the IPL message was garbled to "IPL O". The 'K' vanished! A clock domain crossing glitch during the IPL-to-channel handoff. The K was there, then *poof*. Classic FPGA debugging moment.

Milestones in 4 days

| Day |           What Worked                  |
|-----|----------------------------------------|
|  0  | Concept, design decisions              |
|  1  | Video controller, IPL loader           |
|  2  | CPU executing instructions             |
|  3  | Full channel I/O with multiple devices |

From nothing to mainframe-style TIO polling loops in 72 hours. Not bad for an FPGA project built during evening tea sessions.

Tomorrow: PS/2 keyboard integration. Then this machine becomes interactive.