The Brain Awakes

 First CPU Instruction Executed on Real Hardware

Today the GMS 2050 CPU executed its first instruction. Actually, its first four instructions:

 ORG  200h
        SIO  10h              ; Start I/O
        TIO  10h              ; Test I/O
        LPSW [WAITPSW]        ; Load wait PSW → halt

WAITPSW:
        DD   000200h          ; Instruction Address
        DB   00h              ; Condition Code
        DB   01h              ; Wait bit = 1
        ...

The LED turned off. That might sound trivial, but it meant: the CPU decoded SIO, the CPU decoded TIO, the CPU decoded LPSW, and then stopped — because the Wait bit was set in the PSW. The LED was wired to the inverse of Wait. LED off = CPU waiting = everything worked.

The Program Status Word

This is where S/360's elegance really shines. Context switching? It's one instruction: LPSW. Load a 64-bit word from memory, and instantly you have a new instruction address, new condition code, new interrupt mask, new everything. RISC-V needs 50+ instructions to save and restore context. S/360 does it atomically in one.

I finally understand why IBM's engineers made certain choices. When you implement it in hardware yourself, the "why" becomes obvious.

What's actually implemented

- SIO (9Ch): Start I/O — pokes the channel, doesn't do much yet
- TIO (9Dh): Test I/O — returns "channel available" 
- LPSW (82h): Load PSW — the magic context switch
- NOPR (07h): No operation — for padding

The Multiplexor Channel is still a stub. But the CPU runs. It fetches, decodes, and executes. That's the milestone.